Nowadays, in the mainstream of integrated circuit production, a low voltage logic circuit and a high voltage semiconductor device are implemented on the same integrated circuit chip. For providing effective isolation between adjacent electronic components, in the low voltage logic circuit and a high voltage semiconductor device, an isolation structure is usually formed in the integrated circuit chip to separate adjacent electronic components from each other. As known, a shallow trench isolation (STI) structure is one of the most popular isolation structures. Moreover, the shallow trench isolation structures of the low voltage logic circuit and the high voltage semiconductor device are simultaneously produced in the same fabricating process.
As the device size of the low voltage logic circuit is gradually developed toward miniaturization because of the process progress, the width and the depth of the shallow trench isolation structure are reduced. If the dimension of the shallow trench isolation structure of the high voltage semiconductor device is identical to the dimension of the shallow trench isolation structure of the low voltage logic circuit, the isolation efficacy of the high voltage semiconductor device is unsatisfied. Therefore, there is a need of providing an improved fabricating method of a shallow trench isolation structure.